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Old 24th May 2022, 5:58 pm   #121
ScottishColin
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Default Re: Perth PET

Apologies.

Reversed them now.

Pins 26,27,28,30 & 32 at c. 5.4v

Pins 29,31 & 33 show c. 0.4v.

Should they have zero voltage or is 0.4 ok?

Colin.
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Old 24th May 2022, 6:05 pm   #122
SiriusHardware
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Default Re: Perth PET

0.4V is OK because they are not bolted to 0V, they are connected via resistors which allows them a little bit of, but not too much, freedom. As mentioned before the reason we use resistors is in case the CPU somehow gets into data-output mode in which case it would not be a good idea for the data lines to be hard-connected to 0V and 5V.

Assuming all of those voltages are 'static' (steady), can you now power up and look to see if there is a steady squarewave on CPU pin 9 (A0) and if there is, look for these frequencies on the CPU address pins as originally found by you at the same stage in your earlier thread. Expect only random characters on the screen during this phase as the code which normally clears the screen and prints the initial greeting is not being executed.

Code:
Address line         Pin          Frequency
A0                   9            250Khz
A1                   10           125Khz
A2                   11           62.5Khz
A3                   12           31.25Khz 
A4                   13           15.63Khz 
A5                   14           7.813Khz
A6                   15           3.096Khz
A7                   16           1.953Khz
A8                   17           976.6Hz
A9                   18           488.3Hz
A10                  19           244.3Hz
A11                  20           122.1Hz
A12                  22           61.05Hz
A13                  23           30.53Hz
A14                  24           15.26Hz
A15                  25           7.632Hz
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Old 24th May 2022, 6:35 pm   #123
ScottishColin
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Default Re: Perth PET

All frequencies are as above.

Colin.
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Old 24th May 2022, 6:49 pm   #124
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Default Re: Perth PET

That's reassuring, as it suggests that the CPU is OK and executing at least one intruction correctly.

Now look for the same frequencies on the buffered BA0 to BA15 address lines, all of those lines should have good strong, clean 0v-5V waveforms on them.

Code:
Sig	IC	Pin

BA0	UC3	18
BA1	UC3	3
BA2	UC3	16
BA3	UC3	5
BA4	UC3	14
BA5	UC3	7
BA6	UC3	12
BA7	UC3	9

BA8	UB3	18
BA9	UB3	3
BA10	UB3	16
BA11	UB3	5
BA12	UB3	14
BA13	UB3	7
BA14	UB3	12
BA15	UB3	9
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Old 24th May 2022, 6:56 pm   #125
ScottishColin
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Default Re: Perth PET

All matched as above with square waves. I had to reduce the time/div to pick up the smaller frequencies but they're all there.

Colin.
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Old 24th May 2022, 7:06 pm   #126
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Default Re: Perth PET

OK, now you need to dual-wield and look at pairs of PROM chip select pins.

with both traces enabled, look at the following pairs of IC pins at the same time

UD9 pin 20 and UD8 pin 20
UD8 pin 20 and UD7 pin 20
UD7 pin 20 and UD6 pin 20

The signals you see there should be mostly high, momentarily low, and in each case the two momentary-low chip select signals should be slightly staggered / offset, you should never see both low at the same time.
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Old 24th May 2022, 8:25 pm   #127
ScottishColin
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Default Re: Perth PET

Working exactly as you described.

Colin.

Quote:
Originally Posted by SiriusHardware View Post
OK, now you need to dual-wield and look at pairs of PROM chip select pins.

with both traces enabled, look at the following pairs of IC pins at the same time

UD9 pin 20 and UD8 pin 20
UD8 pin 20 and UD7 pin 20
UD7 pin 20 and UD6 pin 20

The signals you see there should be mostly high, momentarily low, and in each case the two momentary-low chip select signals should be slightly staggered / offset, you should never see both low at the same time.
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Old 24th May 2022, 9:11 pm   #128
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Default Re: Perth PET

Good, that means the address decoder is at least nominally working.

Let's do a quick check on the read / write signal which emerges from the CPU, passes through several gates and (if none of the earlier gates are faulty) should be available on UA3 pin 8, also look at the read enable signal for the system data bus buffers on UE9 and UE10 pin 19 (signal on those last two should look identical)
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Old 24th May 2022, 9:24 pm   #129
ScottishColin
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Default Re: Perth PET

UE9 and UE10/19 check out nicely together.

UA3 pin 8 goes straight to 5.4V and stays there however.

Colin.

Quote:
Originally Posted by SiriusHardware View Post
Good, that means the address decoder is at least nominally working.

Let's do a quick check on the read / write signal which emerges from the CPU, passes through several gates and (if none of the earlier gates are faulty) should be available on UA3 pin 8, also look at the read enable signal for the system data bus buffers on UE9 and UE10 pin 19 (signal on those last two should look identical)
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Old 24th May 2022, 9:32 pm   #130
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Default Re: Perth PET

Work back through the following points on the R/W signal chain until you find activity, and report back.

UA3 pin 9
UA3 pin 12
UA3 pin 13
UA10 pin 4
UA10 pin 3
6502 pin 34
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Old 24th May 2022, 9:47 pm   #131
ScottishColin
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Default Re: Perth PET

No square waves anywhere. |Voltages as below:

UA3 pin 9 - 0v
UA3 pin 12 - 0v
UA3 pin 13 - 5.3v
UA10 pin 4 - 5.3v
UA10 pin 3 - 4.4v
6502 pin 34 - 4.24v

I powered off and checked continuity from pin 34 for the 6502 to the pin 34 pad on the motherboard and that's good so I don't think it's the NOP device getting in the way of pin 34's connection.

Colin.


Quote:
Originally Posted by SiriusHardware View Post
Work back through the following points on the R/W signal chain until you find activity, and report back.

UA3 pin 9
UA3 pin 12
UA3 pin 13
UA10 pin 4
UA10 pin 3
6502 pin 34
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Old 24th May 2022, 10:00 pm   #132
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Default Re: Perth PET

We may be chasing down a red herring here as the R/W line is probably in the 'high' state at all times unless the CPU attempts to write to something, at which point it will go momentarily low. At the moment we are forcing the CPU to do read-only operations.

Have a look at the general state of the unbuffered motherboard data lines DA0-DA7 but this time on CPU pads 33-26 on the motherboard, not on the CPU. Each one will probably be a mess of activity, what you are looking for is one which looks substantially different to the others in terms of the shape or the height of the signals.

Last edited by SiriusHardware; 24th May 2022 at 10:11 pm.
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Old 24th May 2022, 10:14 pm   #133
ScottishColin
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Default Re: Perth PET

Not easy to get in there with the NOP device, but I saw square waves on every pad.

Colin.
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Old 24th May 2022, 10:19 pm   #134
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Default Re: Perth PET

Now try looking at the buffered data lines on the 'other side' of UE9 / UE10, specifically,

Pins 18, 16, 14, 12 of UE9

and

Pins 18, 16, 14, 12 of UE10

Anything out of the ordinary?
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Old 24th May 2022, 10:50 pm   #135
ScottishColin
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Default Re: Perth PET

No - good square waves that are the same on each pin and compare the same across the ICs (for example UE9 and UE10 pin 18).

Colin.

Quote:
Originally Posted by SiriusHardware View Post
Now try looking at the buffered data lines on the 'other side' of UE9 / UE10, specifically,

Pins 18, 16, 14, 12 of UE9

and

Pins 18, 16, 14, 12 of UE10

Anything out of the ordinary?
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Old 24th May 2022, 11:07 pm   #136
SiriusHardware
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Default Re: Perth PET

Okay, will have to have a think about where to go next. (As usual, everyone else please pitch in with ideas).

The unbuffered and buffered address bus look normal as does the address decoder which selects the PROMs which in turn present their data directly to the CPU (not via buffers).

The Test EPROMs (Slothie's, Daver2's) carefully avoid using external RAM until they are sure that zero page RAM at least is working and if it isn't they report that by writing to the video RAM.

But even that basic environment apparently is not working, so at the moment we have to say that either the CPU is unable to read and execute code from PROM, or code is running but is unable to report results because it can not pass anything through the buffers to the video RAM. The video system itself is running OK, happily rendering the random startup content of the video RAM onto the screen.
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Old 25th May 2022, 10:47 am   #137
ScottishColin
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Default Re: Perth PET

Couple of quick photos to show where we are without the NOP test socket installed.

Photo 1 is a consistent screen whether I have the 6502 fitted with original ROMS, the 6502 fitted with DaveR2 test ROM as well, or the 6502 fitted with Slothie test ROM fitted.

Photo 2 is with the Tynemouth board fitted, a different (new to me) 6502 and ROM and RAM provided off the Tynemouth board (Basic 4 and motherboard ROM/RAM bypassed).

You can just see on photo 2 that the normal screen is partially there in the top left hand corner, along with a flashing cursor but that the keyboard does not work at all.

Colin.
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Old 25th May 2022, 5:17 pm   #138
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Default Re: Perth PET

Since the Tynemouth board is eliminating the PET's own RAM and ROM from the equation we seem to have come back to looking for an intermittent problem somewhere in the vicinity of the video, PIA/VIA or CPU logic circuitry.

I know that the PET is generating characters and some are being held in video RAM but the two video RAMs (previously replaced!) are now socketed so it might be worth checking them by substitution if Colin has any spares. The same applies to the VIA and PIAs particularly the keyboard PIA (UC7). I don’t think any of the three have been replaced before. There are quite a few socketed logic chips dotted around the circuit now and some of them could again be checked by substitution if Colin has any in his spares collection. Of course a poor connection somewhere is still a strong possibility but I’m sure Colin will keep his eyes open and meter in hand.

I know I’m fumbling around in the dark but my excuse is that intermittent faults are often really difficult to track down. Hopefully Sirius will come up with some more logical/methodical ideas on how to proceed as well.

Alan
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Old 25th May 2022, 5:45 pm   #139
Mark1960
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Default Re: Perth PET

I was just wondering if the high voltages, up to 5.49v, reported by Colin in earlier posts were indicating a supply voltage issue or just a limit of the accuracy of his dmm.

5.5v would be the maximum recommended supply voltage for TTL and possibly some of the other ICs in the PET.

If there are two separate 5v supplies a large offset between them could cause some issues where two groups of ICs are at different supply voltage. I don’t remember if the PET has this type of supply.
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Old 25th May 2022, 6:48 pm   #140
ScottishColin
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Default Re: Perth PET

The voltage readings came from the scope. I could re-read with the meter; I suppose it's impossible to know which is likely to be more accurate?

Colin.

Quote:
Originally Posted by Mark1960 View Post
I was just wondering if the high voltages, up to 5.49v, reported by Colin in earlier posts were indicating a supply voltage issue or just a limit of the accuracy of his dmm.

5.5v would be the maximum recommended supply voltage for TTL and possibly some of the other ICs in the PET.

If there are two separate 5v supplies a large offset between them could cause some issues where two groups of ICs are at different supply voltage. I don’t remember if the PET has this type of supply.
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