Mk14 vdu

[Timbucus]

Actually you don't have to sit long after power up to catch it being naughty either... probably in this case though as SCIOS is down at the bottom of F00-F10 any corruption is lower in RAM so does not show up but, could account for the occasional corrupt 7 segment thing we sometimes see at D00?

[Slothie]

Originally Posted by Timbucus

Actually you don't have to sit long after power up to catch it being naughty either... probably in this case though as SCIOS is down at the bottom of F00-F10 any corruption is lower in RAM so does not show up but, could account for the occasional corrupt 7 segment thing we sometimes see at D00?

Attachment 219389

SCIOS also uses FFC/D/E/F for pointer storage doesn't it?

I'm a bit confused, in the oscilloscope images, the top trace is the output of your NOR gate, what is the bottom one? NENIN? If so, all the writes seem to be while the SC/MP is in control, so what the VDU is doing can only be forcing bad data onto the data/address buses. Its a puzzle....

[Timbucus]

Originally Posted by Slothie

SCIOS also uses FFC/D/E/F for pointer storage doesn't it?

I'm a bit confused, in the oscilloscope images, the top trace is the output of your NOR gate, what is the bottom one? NENIN? If so, all the writes seem to be while the SC/MP is in control, so what the VDU is doing can only be forcing bad data onto the data/address buses. Its a puzzle....

It does use the upper parts but, only on entry and exit I believe so would not access them in normal running.

Yes the traces are NENIN bottom sorry should have been explicit.

I agree it can only be bad data - I have a theory that as the VDU starts to assert address bus and _CE1/2 for read there is enough on NWDS from the fact it seems to hold around 1v in SC/MP tri-state. That runt is big enough to trigger a write I think.

[Mark1960]

So with the 10k pullup on NWDS there seems to be two different issues. A sharp pulse when NENIN is switched high and the runt, both with slightly different symptoms.

It seems the sharp pulse when NENIN is switched high might be fixed by the lower pullup on NWDS.

The runt doesn’t seem to be fully switching to high level, so possibly one or more of the inputs between 0.8 and 2v at that time. Is is possible to see whats happening at each of the three inputs at the time of the runt?

[Timbucus]

This is a wide view of NWDS, _CE2 and _CE1

[Timbucus]

Well I thought I would go in for a closer look at these while doing so I noticed there is a very short pulse slightly higher in level as well - so I was able to trigger from that level
This is what the runt looks like over NWDS and one of the CE lines...



and the other pulse:



and that pulse over _CE1 and _CE2

[SiriusHardware]

I've been out all day and have only just been chased back indoors by stormy weather, so I've just caught up. I have a few 74LS27s at work so I'll plant one on a bit of veroboard with flying leads tomorrow and see if I can replicate some of your results.

One instance where you caught a write to 0Fxx with SCIOS idling, I would say that is normal, if you have the VDU enabled with 0Fxx displayed top half you can see that SCIOS is continually modifying at least two locations in the range 0F00-0F11 where it keeps its 'system variables', so I would expect to see regular writes to 0Fxx when NENIN is not asserted by the VDU.

Again for the purposes of clarity, can I suggest that when we post images of captures, for each image posted we should explicitly state which signals (or which combinations of signals) are being shown on the upper and lower trace in the image and any other pertinent information such as the 'time scale' of the capture, ie, one video frame, one video line, etc. I will try to do this from now on.

[Timbucus]

Indeed will try to do so - on the scios one look at the second pulse it is when NENIN has been asserted and cannot be the VDU doing the write or it was but it continues after the bus request so the PIC is likely to be changing the bus...

[SiriusHardware]

Post #745, if these are all triggered from the shark-fin and looking at _NWDS, _CE1 and _CE2 in turn, they appear to show that you get the 'fin' only when all three are high (inactive) for a significant amount of time. This 'ramp' may coincide with the address buses drifting off to some intermediate level when they are allowed to go tristate.

[SiriusHardware]

Originally Posted by Timbucus

on the scios one look at the second pulse it is when NENIN has been asserted and cannot be the VDU doing the write or it was but it continues after the bus request so the PIC is likely to be changing the bus...

.

Yes, I see that. I'll see if I can also capture that as well.

[Timbucus]

These images (of LS27 XOR of NWDS,2CE over NENIN) were a bit blurred so I did not originally post them but, I think they are useful looking at the sharktooth runt (rather than the needle pulse which is not visible at this level) in context shows what I believe is the start of the Video frame where Karen gives the SC/MP quite a bit of time and the sawtooth runt is ALWAYS in the same place over the slightly longer NENIN assertion before the first line of pulses which is shown zoomed in on the second picture.



I cannot give a better context for the location of the needle runt pulse as I don't have any wider captures but, it is about .1 or .2v greater than the sharktooth. (all the captures are 2v per division). Hopefully this helps would be great if you get both the sawtooth and the needle pulses at roughly the same levels.

Edit:I should also add that all of these are without the 10K pullup on the address line we were experimenting with earlier in the thread that served to clean up the signal on the one B00 _CE.

[SiriusHardware]

I put together a 74LS27 _NWDS / _CE1 / _CE2 combiner at work today but also took my 7.5V regulated supply (which I run the issue VI from) into work today to effect a minor repair and, while I brought the 74LS27 gizmo home, I forgot to pick up the PSU and bring that back so I won't be able to make progress until tomorrow (Tuesday) now.

[Mark1960]

Originally Posted by Timbucus

This is a wide view of NWDS, _CE2 and _CE1

Attachment 219414Attachment 219415Attachment 219416

Lost our internet yesterday so just catching up.

It doesn’t make sense that the output of the 74ls27 is rising when the three inputs are all high. Is it possible there are very high frequency signals on NRDS, _CE2 and _CE1, beyond the sample rate of the scope? Just wondering if this might be a pwm effect.

[SiriusHardware]

Tim's scope is 100MHz capable so I would like to hope it can catch anything that a 1970s microprocessor system can throw up.

I think that on that first rising edge of NENIN, the SC/MP dives off the address bus, but the VDU does not jump onto it immediately. That gives the address lines time to float to whatever intermediate level they feel like, although it takes time, about 55uS from the rising edge of NENIN to the peak of that sharkfin.

The address decoding for _CE1 and _CE2 is derived only from A8-A11 so any intermediate levels on those lines translate to intermediate levels on the _CE1 and _CE2 lines, as has been seen.

Our 74LS27 is getting two of its three inputs from the _CE1 and _CE2 pins, one or both of which may be at a very illogical level, and the 74LS27 then tries to come up with some sort of result.

Ian's suggestion of trying three diodes, maybe schottky signal diodes, and a weak pulldown resistor as a 3-input 'OR' might provide some degree of illumination because that would remove the effect of the logic input level threshold of the 74LS27, which may be confusing the issue. I don't know if I'm explaining it very well - when looking at the output from the 74LS27 we are looking at the result of how that IC responds to what are possibly very odd levels on at least two of the pins, so eliminating the 74LS27 and deriving the combined signal directly from _NWDS, _CE1 and _CE2 might prove more informative.

[SiriusHardware]

Anyway, the fact that the sharkfin occurs when _NWDS, _CE1 and _CE2 are all inactive suggests to me that we don't need to worry about it. All we're seeing there is the result of the address bus 'relaxing' over time when it has not been driven either by the SC/MP or by the VDU for tens of microseconds.

[Timbucus]

Originally Posted by SiriusHardware

Anyway, the fact that the sharkfin occurs when _NWDS, _CE1 and _CE2 are all inactive suggests to me that we don't need to worry about it. All we're seeing there is the result of the address bus 'relaxing' over time when it has not been driven either by the SC/MP or by the VDU for tens of microseconds.

Indeed but the captures that concerned Mark as being high frequency (perhaps induced from the switch mode PSU maybe?) were where I looked at the very short higher pulse over each input line in turn so we can see what is underlying it on the chip.

https://www.vintage-radio.net/forum/...&postcount=745

I was looking at the F00 chip and obviously it was not the same moment as it was three captures after moving the other scope probe from NENIN to each of NWDS, _CE1 and _CE2 in turn - but, you can see the top image of the pulse on the output of the LS27 is the same shape in each so no reason to suspect I did not capture the same type event - I may try now to capture the same three signals under the sharktooth - I may not be able to get it working again tomorrow as I have to clear the desk to work from home...

[Slothie]

Originally Posted by SiriusHardware

Ian's suggestion of trying three diodes, maybe schottky signal diodes

Standard 1N4148 diodes have a switching time of 4nS so they are plenty fast enough, and if you're making a trigger for a scope the 0.6v drop isn't significant.

[SiriusHardware]

Bearing in mind the fact that the _CE1 and _CE2 lines may have logic 0, logic 1, or potentially any level between those two on them, I wanted to be able to see if there was anything at all - anything over 0.1V anyway - on any of the lines.

My offboard regulated PSU is a linear one, I don't trust SMPSUs with old retro tech like this unless their 0V is connected to mains earth - so whatever results I eventually see won't be down to switching noise from the PSU.

[Timbucus]

Well you probably won't get the sawtooth - it has taken me ages to get a reliable setup and I had to provide a ground clip off the capacitor to the breadboard so I wonder if that was some induced noise in the ground plane as Mark suggested as the connection on the top of the chip was poor - I have ordered a set of clips as had enough of this fiddling. Maybe it was reflections of the short spike - square waves are messy...

I still have the short duration spike though on the output of the LS27 combined signals and it seems to be in the same place over the top of what I assume is the start of the video frame... This is the usual summed LS27 trigger in yellow over the NENIN signal - using the scopes zoom option to see that it is after the NENIN assertion.



The amplitude of that pulse seems to go up and down a little (sine wave beat with something?) and the rate of the change of the character seems to be in sync with it - judge for yourself here is a video I was thinking to extract the frames to prove the letter changes in sync with the pulse...

https://youtu.be/8miKNN05SVg

I know I need to make a nice Linear supply like you... Maybe I will bypass the Reg and use the top half of the SCRUMPI one I built.

I will see if I can capture the underlying signal state of each CE and NWDS next when the pulse happens.

[Timbucus]

Here they are a little darker so you can read the data 2v per division 500ns so close in. In order of picture LS27 sum over the _CE1, _CE2, NWDS for three similar pulse events.