Karens PAGE2.SYS relocated to PAGE3 for NIBL-E systems

[Phil__G]

Having finally built a 'full house' SC/MP based on Ronald Decker's design on Kris Sekula's PCB, I've been busy on the software and presently have a system that includes
(in location order) KitbugPlus, NIBL-E, Karen's PAGE3.SYS, and Erich Küster's NIBL-FP, all running at 2400N81.

PAGE2.SYS (now PAGE3.SYS) if you recall is Karens very clever integrated assembler and more for NIBL (now for NIBL-E). It appears to NIBL-E as a basic program, but fills the remainder of page 3 with magic and in addition to the assembler provides a good few 'monitor' commands including print, dump, and cassette load & store! Its ongoing, of course - Karen included an aux printer port which could be repurposed for the Aliexpress receipt printer we found recently.

In order to run KB+ at its 'native' address (0000h) there is a small change to Ronald's memory map in that page zero, which Ronald had as 4k of ROM, is now split 2k ROM for KB+ and 2k RAM for variables, scratchpad & stack. Having KB+ in its natural location means that monitor routines like GECO:, PUTC: etc are at their 'proper' locations.

Page 1 (1000-1FFF) is NIBL-E in rom, in fact from page one upwards its mapped exactly like Ronalds, though now having 2k decodes available I'm tempted to recover 6k of ROM from the 8k allocated to the 8255 PPI. Ronalds address decoding is 8 blocks of 8k using a 74LS138 on A13,14,15, so instead I've used a gal16v8 to make it more flexible - memory-map changes are quick and easy.

Have to say, Benny (Audiokit) and Kris have both been amazingly helpful and patient, especially during the early stages, testing code for me before I had the hardware

I'll tidy-up and post this on my page in the hopes that other 'Ronald Decker' builders might find it interesting although note its not Ronalds posted rom image, there have been many changes throughout. Note also that Ronald hast posted the corrections to his diagram which shows /RAMCS & /ROMCS swapped.

Kitbug+ > G1000

PAGE3
*ASM 5
PASS 1:
PASS 2:

*NIB

NIBL
>PAGE =5
>LIST
5 PRINT"PAGE3.SYS test"
6 PRINT"Flash an LED on Flag 2"
7 LINK TOP
10 ASM
20 LDI #FF
30 DLY #FF
40 CSA
50 XRI 4
60 CAS
70 JMP $20

The assembled code is at TOP so just needs a LINK TOP to run. Theres so much to learn from Karens projects

Kris's PCB is brilliant, but to be fair I'll leave the presentation to Kris, all I will say is that it makes a Ronald Dekker build so easy, it has everything you need for a 'full-house'' SC/MP
Cheers
Phil

[Phil__G]

Heres Karens PAGE3.sys
Its a binary file so load using S3000 in KB+ (remember to tick the 'binary' box in Teraterm)
then G1000 to go into NIBL-E
if it doesnt start automagically (it should) then do PAGE=3 and RUN

Karens doc also attached for the PAGE2.SYS chapter, remember we are 1000h above NIBL when using NIBL-E

PAGE3.sys is rommable if you prefer it to permanently occupy the system's page 3

[Phil__G]

Originally Posted by Phil__G

PAGE3.sys is rommable if you prefer it to permanently occupy the system's page 3

With a quick & simple gal change I've now got PAGE3.sys in ROM, it runs exactly the same but its resident immediately on power-up, in fact it auto-runs as soon as you enter NIBL-E.
This is a really nice setup, with KB+, NIBL-E, PAGE3 and NIBL-FP all in ROM! This would have been the moon on a stick back in 1976!

I have a few PCBs to give away, first come first served by PM

Originally Posted by Phil__G

Note also that Ronald hast posted the corrections to his diagram which shows /RAMCS & /ROMCS swapped

What I meant to say was
Note also that Ronald hasn't yet posted the corrections to his diagram which still shows /RAMCS & /ROMCS swapped

[Realtime]

Originally Posted by Phil__G

Heres Karens PAGE3.sys
Its a binary file so load using S3000 in KB+

PAGE3.sys is rommable if you prefer it to permanently occupy the system's page 3

That’s working great, thanks Phil. Installed on the LCDS along with KB+ and NIBLE. The LCDS uses the lower half of Page7 for its own monitor program so I’m limited to pages 2-6 for NIBLE.

[Phil__G]

Excellent - Karen would have been really chuffed to have PAGE2(3).SYS running on a genuine LCDS!

I freed the unused inputs on the LS573 address latch (Kris's PCB U4 pins 6,7,8,9) and wired them to D4-D7.
This makes four signals available, R=read cycle, I=instr fetch, D=delay in progress, H=halt.
These are wired to a 5-way socket header (4 signals & gnd) - I've repurposed the unused RS232 9-way
pads so it looks quite neat, the 5 connections left to right are R, I, D, H, & Gnd
I put a 5v LED on the latched D output and now it indicates wherever in the program there is a delay!

Elektor identified an 'inconvenience' with NIBL-E in that it doesnt clear unused pages, often if you
enter NIBLE and do say PAGE=5, LIST you get a screen of rubbish.
This transfers to PAGE3.SYS when you do a DIR, but its not PAGE3's fault!
I have a Teraterm script that goes

PAGE=2, NEW, PAGE=3, NEW, PAGE=4, NEW, PAGE=5, NEW, PAGE=6, NEW, PAGE=7, NEW

...and that clears it up for now, but a proper fix is on the 'todo' list

Originally Posted by Phil__G

I have a few PCBs to give away, first come first served by PM

Here's my 'delay in progress' LED...

[Mark1960]

Hi Phil,
Whats the memory map for eprom? Is NIBL-FP top 8k?

Could page 3 be moved to high memory instead of using a NIBL page?

It might be best not to clear ram pages, it might be usefull to use nvram.

[Phil__G]

Hi Mark, PAGE3.SYS masquerades as a NIBL program so it has to be a valid NIBL page, whether high or low. Additionally it uses the previous page (page 1 for PAGE2.SYS, page 2 for PAGE3.sys) for the symbol table, which is also hidden in a NIBL program.
Wherever it lives it needs two valid NIBL pages, and since its intended to auto-run, page 2 & 3 are appropriate.

The overall system memory map is now:

Page zero:
0000 - 07FF (2k) ROM - KitbugPlus
0800 - 0FFF (2k) RAM scratchpad, variables & stack

Page 1:
1000 - 1FFF (4k) ROM - NIBL-E

Page 2:
2000 - 2FFF (4k) RAM - general use and PAGE3 symbol table

Page 3:
3000 - 3FFF (4k) ROM - PAGE3.SYS

Page 4:
4000 - 4FFF (4k) RAM

Page 5:
5000 - 5FFF (4k) RAM

Page 6:
6000 - 6FFF (4k) RAM

Page 7:
7000 - 7FFF (4k) RAM

Then:

8000 - 9FFF (8k) ROM unused at the moment
A000 - BFFF (8k) very wasteful 8255 PPI decode (will fix this)
C000 - CFFF (4k) ROM unused
D000 - FFFF (12k) ROM - NIBL-FP floating point basic

Cheers
Phil

[Phil__G]

I found Karens update to her PAGE2.SYS program,
I've converted it to page 3, load using KB+ command S3000 with Teraterm 'binary' ticked

[Mark1960]

Erich’s github has a monitor located at C000 that you might want to try in the unused part of rom. Not sure how it differs from kitbug or if it just provides a monitor for systems with NIBL in page 0.
https://github.com/ekuester/SCMP-INS...IC-Interpreter

Is it usefull to have Kitbug and NIBL-E both in the memory map instead of switchable choice between Kitbug and NIBL in page 0? NIBL-E uses one page, then Page3 seems to use two more.

Does NIBL-FP have any dependency on NIBL or Kitbug? Or it just needs some way to call its start address?

Planning a simple system with switch selectable memory map, so any thoughts on options that might be usefull?

[Phil__G]

Hi Mark, yes for me its really convenient to have both, especially whilst working on NIBL itself or using M/C from NIBL
You cant readily switch NIBL with Kitbug or KB+ because both need ram in page zero accessible by wrap-around, whereas NIBL needs
the full page zero in rom - so you'd need to switch memory maps as well as rom content!
If you recall, NIBL-E came about precisely because Elektor's monitor Elbug occupied page zero.
If you did need more memory, the gal makes it so flexible, the two PAGE3.SYS pages can be used as ram, with PAGE3 loaded as & when desired.
I find theres more than enough for me so I put PAGESYS in rom, its fun, I'm really enjoying it as it is
NIBL-FP is completely independent, has its own I/O, which I've set to 2400N81 to match KB+ and NIBL-E
Apparently Fred Van Kempen has an improved FP basic which I havent looked at yet, too busy with recent projects...
Mike's SC/MP Max on Oldmicros might suit you, with its 64k of NVRAM acting as rom & ram giving a totally flexible memory map:
https://sites.google.com/view/oldmicros/sc-mp-ii-max
I have one on the bench right now, half-built!
Cheers
Phil

[Mark1960]

Switching between 4k rom and 2k rom + 2k ram is simply connect or disconnect A11. Ram chip select is nand of rom and io select. I had a fairly simple plan to use 74hct193 to latch address page, borrow out to select rom, carry out to select io, nand of both to select ram.

Then you reminded me of NIBL-FP so I can’t have page F for io.

[Phil__G]

Many ways to skin a cat but I'm really happy with this configuration, plans are afoot for the ultimately
flexible system using 64k ram & 64k rom chips with a gal to easily interleave any memory map you like
Incidentally, I wonder if anyone seen a multi-page NIBL program? ever?

The PAGE3 project has been hampered by the fact that my laptop has a faulty '3' key, so you can imagine
how much fun its been relocating everything to 3000h using 'ALT-51' ...

[Realtime]

Currently Kitbug+, NIBLE and Page3.SYS all working perfectly on the LCDS at 2400 baud, but not a sausage from NIBL-FP (at #D000). I read that NIBL-FP uses page 7 RAM for it's stack etc. Because the LCDS needs page 7 for it's own HW/FW operation does that mean I can't run NIBL-FP on it?

And, because I like to stand on the shoulders of giants (Phil__G ), is NIBL-FP modified for 2400 baud available yet for download?

[Phil__G]

You're well aware that you're streets ahead of me Ian but your encouragement is appreciated!
FP as far as I can tell (its a lot of code) is completely independent and unless LCDS was running interrupts FP wouldnt even know LCDS was there. All its I/O is separate and doesnt rely on any external routines. So it should run regardless of any other claim to page 7. The only changes I've done to Erich's code is to the I/O (putc & geco) so it ought to be ok...
Is your rom continuous D000-FFFF? did you remember not to start FP at the start of the eprom? I mean for example D000 is 4k up in a 16k chip located C000-FFFF?
If you dump D000 onwards does it agree with the hexfile?

My SC/MP page was getting unwieldy so I've split it into a page for Karens emulations and a 'real' INS8060 SC/MP page.
The FP file is at the very bottom of the 'new' SC/MP page. If necessary, appending a variable like ?k=7 to the url will force your cache to refresh.
http://philg.uk
FP has only recently drawn attention so dont take my edits as definitive, as I've been reminded only today, its very likely others will improve on it!

Cheers & thanks again
Phil

[audiokit]

I have the SC/MP variant of Phil's programming.
I made the schematic as shown on the page of Ronald Dekker (errors fixed) and FBASIC (and Kitbug+. NIBL-E, page 3) is running fine on 2400 Baud.
FBASIC is programmed in the 27512 eprom and uses address C000 to FFFF.
I don't think it needs a page as scratchpad, there is really code on page 8.
I see an area with only FF from C000-D000. after that D000 to FFFF is all coded.
So page 7 and 8 are occupied by code for FBASIC. I don't know if there is a posibility to place it further down in the area that is used for RAM now. I could give it a try by switching some glue logic again.
Regards, Benny

[Realtime]

Originally Posted by Phil__G

My SC/MP page was getting unwieldy so I've split it into a page for Karens emulations and a 'real' INS8060 SC/MP page.
Phil

Got it now thanks - must have been hidden behind the old cache. I will give that a go tomorrow and check the addressing in ROM

[Phil__G]

Thanks Benny
Ronalds (corrected) design shows eight x 8k decodes, which are variously gated to RAM & ROM.
The two uppermost of the 8k decodes are allocated to 16k of ROM at C000-FFFF,
of which FP uses 12k, D000-FFFF. As Benny says, C000-CFFF is 4k of empty ROM reading FF.
I'm not sure what Ronalds intention was for the 8k of ROM at 8000-9FFF, on mine its empty (FF)

The GAL decoder replicates Ronalds from 1000h (PAGE1) upwards but differs only in that it splits
PAGE Zero into half ROM, half RAM - otherwise the memory map is the same as Ronalds.
(though I recently changed PAGE3 from RAM to ROM for Karens PAGE3.SYS,
FP might not expect this if it thinks 1000h upwards is RAM))

Is your LCDS config similar to this Ian?

Cheers
Phil

[Realtime]

I’m pretty sure I implemented the GAL memory map in the LCDS CPLD but will double check. I’m going to build the Ronald Decker pcb that you sent me, at the weekend, and demonstrate everything running on that. Then I’ll look again at the LCDS.

[Phil__G]

I've noticed that entering programs into NIBLFP is an incredibly slow process,
as a line is entered, the prompt often doesnt return for a few hundred ms

[Phil__G]

Even if the code was instant, FP would still need an absolute minimum character delay of 5ms because GETASC: doesnt echo bit-by-bit like GECO: does, instead it receives the whole character then re-transmits it for echo at PUTASC: - so you cant start sending again until the echoed character is finished, 5ms minimum at 2400 baud.
In practise, the code not being instant, actual required character delay seems to vary - for CALENDAR.BAS I've found anything less than 200ms character and 1000ms line delay will give errors, eg line 540 would be entered as line 40.
The weird thing is, it seems to struggle at the beginning of longer programs - even though it is unaware how long the program is going to be.
But speed aside, having a floating-point basic for the SC/MP is great!

Edit: cant get MODulus to work?