Karen's most recent SC/MP

[Phil__G]

More progress to report, with changes to the Get Effective Address macro the 2019emu now running pretty much anything anywhere in memory, using the S command fast serial loader, it loads & runs KtbugPlus, NIBL, NIBL-E, all the NIBL programs I've tried, the machine-code games like Life & such all org'd at different addresses in different pages, all the backward-reference things seem to be working ok.
Almost perfect
However...
One remaining oddity is that to run NIBL-E I have to enter G1001 rather than 1000 so the changes to 'get effective address' are not yet 100%. This seems to happen only on a page boundary 1000h, 2000h, etc
Much better, quite usable as a very cheap general purpose 32k SC/MP, but still a WiP
Cheers
Phil

[Mark1960]

Were you able to keep the cycle times correct with those mods?

I was wondering if it might be worth trying a PIC16F18877. This is still in active production, has a 32MHz internal oscillator, which might allow the cycle time to be padded to match the 8060 cycle times. Then maybe a TQFP44 part on an adapter pcb to 40 pin DIL could be made to look like a 40 pin chip.

[Phil__G]

Unfortunately not as theres more code in there Mark, but once its sorted I could look at that, the 2400 serial terminal & fastloader timings are unchanged and they work fine.
These problems would be exactly the same in a 18877 so I'd like to get this fully functional first before moving on
The remaining problem is generic, cos rebooting from NIBL-E needs a LINK 1 rather than the expected LINK 0.
That said, at least it is quite usable now, all over the memory map it runs everything I've thrown at it
Again its only fair to say that in its intended guise, ie a 32k NIBL computer, the original software is fine
Cheers
Phil

[ortek_service]

Originally Posted by Mark1960

>>

I was wondering if it might be worth trying a PIC16F18877. This is still in active production, has a 32MHz internal oscillator, which might allow the cycle time to be padded to match the 8060 cycle times. Then maybe a TQFP44 part on an adapter pcb to 40 pin DIL could be made to look like a 40 pin chip.

I also wondered if a higher pin-count PIC might also allow the implementation of some / all of the currently-absent (nENIN, nENOUT, nBREQ, nHOLD, CONT, nADS ?) pin functions. But unfortunately it seems the 44pin SM packages just have the extra 4 pins as NC / extra power & Gnd.

I did also see that some of the newer PIC16F19xxx? PIC's featured on Microchip's PIC webpage have built in Logic-Blocks, which may be useful in providing some functions in h/w for speed. But these were all in lower pin-counts of only upto 20pins?

And I don't think they make a PIC16F (or PIC18F?) with more pins / GPIO's. So would have to go to the rather-different PIC24F family to get those
- Or to an ARM / ESP32 etc uC, which would provide plenty of I/O's but a rather large job of porting the assembler across (especially getting the cycle times right!)

[Mark1960]

PIC16F18877 makes two more pins available for RA6 and RA7 as the external crystal is not required.

[Mark1960]

What is the issue with Link 0? Is it caused by the emulation executing the halt instruction that is often placed at the beginning of the page. The 8060 needs external hardware to implement halt.

[ortek_service]

Originally Posted by Mark1960

PIC16F18877 makes two more pins available for RA6 and RA7 as the external crystal is not required.

Well that might allow nADS at least.

But would the 32MHz internal oscillator be accurate enough, to not require an external crystal? (Especially if wanting to use a VDU with it?)
(Maybe there is some factory-trimming on these / temperature stability & ageing isn't too bad on these. Internal oscillators used to often only be 1% at best, which was OK for Serial Comms at least)

[Mark1960]

Once you get NADS working you free up four address lines to use for other functions, assuming those four address lines can then be multiplexed on the data. This is probably not going to be easy to implement.

I was wondering if the 12 bit pointer wrap around might be implemented by using a different register in the PIC for the upper four bits of each pointer. This might save a few instructions compared to manipulating the upper four bits of a register.

[Phil__G]

Originally Posted by Mark1960

What is the issue with Link 0?

In a nutshell, its me adding 12-bit "effective address" code to try to better emulate a real SC/MP. Its either correcting overenthusiastically or I've missed a case elsewhere where it also needs to be done WiP. Its all related to pointer 12-bit wrap-around and calculating 12 bit effective-addresses whilst maintaining the high nibble.

[Phil__G]

To get this thread back on topic , ie Karens most recent 2019 NIBL computer, I've just updated the zipfile again: https://www.mccrash-racing.co.uk/phi...picl.htm#k2019
Summary - both BASYS and the disassembler now include a serial fast-loader (full 2400 binary, no delays) and m/code I/O to speed things up. I've also done a version of the NIBL Toolkit for it, relocated to 0x7400 and with the printer routines disabled (theres no SOUT on the PIC). The emulator itself has NIBL at 2400 with the 'bit7 GECO bug' fixed. The PIC runs at 20Mhz which equates to a 4Mhz SC/MP II and NIBL's Flag zero is inverted internally so no external inverter.
Bugfixes: fixed the DAD macro which broke the emulation of DAE and DAI instructions, & the CSA instruction which corrupted STAT. Note Karens diagram shows SenseA grounded - I assume this is a typo, I've left it open.

I was thinking about the price of genuine SC/MP chips now and concluded that Karens two-chip NIBL computer is a very cheap, totally viable alternative to a full SC/MP system like the MGH8060, the Ronald Dekkers and the "SC/MP II Max" - so quick & easy to build and having NIBL, a monitor, disassembler, & the toolkit make it genuinely practical. It just might be my favourite of all Karens gems, I even cased it!
Cheers
Phil

[Mark1960]

SenseA grounded is probably deliberate to avoid leaving it floating input on the PIC. I know interupts are not supported but if they were then SenseA would be active high.

[Phil__G]

I've added an 'OLD' command to BASYS on the KO2019, this is the opposite of NEW and can be used to restore programs after NIBL has cleared a page. I use a 32k NVRAM on the KO2019 which retains programs, but on power-up NIBL still 'clears' its pages.
In fact NIBL overwrites only the first line number (two bytes) and the line length (one byte) on each page, and this is what the OLD command recalculates & inserts.
For familiarity I keep BASYS in page 5, and so I have a simple Teraterm script to restore page 5 (though sometimes I type it manually):

@#5002=0
@#5003=1
@#5004=57

Once BASYS is restored, any other pages can be restored using the O (Old) command.
As usual, much, much quicker & easier to do than to describe, sounds faffy but takes seconds...

https://www.mccrash-racing.co.uk/phi...picl.htm#k2019

[Phil__G]

Two versions of John Conway's 'Life' for the KO2019, load to #6200 using the BASYS S command with Teraterm set to binary with no delays.
Alt-B to break back to NIBL:

[Phil__G]

This version loads to #1120 in PAGE 1 and lists as a pretend NIBL program, it asks for one keyboard character which it uses as a seed for a randomish starting pattern. It loads using the BASYS S command to #1120 followed by PAGE=1 and RUN.
(Just trying to generate some interest here...)