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Old 26th Jan 2023, 5:31 pm   #21
Mark1960
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Default Re: Advanced Mk14 Enhancements

6850 does need some configuration set up by the processor but the 6402 doesn’t. All the option selection on the 6402 can be done with dip switches. Any idea where you are going to locate the uart in memory or are you planning to interface through the 8154?
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Old 26th Jan 2023, 5:50 pm   #22
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Default Re: Advanced Mk14 Enhancements

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6850 does need some configuration set up by the processor but the 6402 doesn’t. All the option selection on the 6402 can be done with dip switches. Any idea where you are going to locate the uart in memory or are you planning to interface through the 8154?
Agree, I have a 6402 on my NASCOM. My main motivation to go down the 6850 route is that I have a few doing nothing and are only 24 pin so will save a bit of board space. I would like to memory map them but there is the issue of not getting in anything else's 'way'.

I'd like have a combined serial and video board (based on Karen's design), but this is very much in the 'minds eye' concept stage currently.
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Old 26th Jan 2023, 6:43 pm   #23
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Default Re: Advanced Mk14 Enhancements

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I'm looking at interfacing a UART \ ACIA to my Mk14...
Only this thread, in which I made an MK14 MIDI output interface using a 6402 intended to be driven from one of the 8154 ports.

https://www.vintage-radio.net/forum/....php?p=1496105

However, I never got around to writing any code to support said UART because forum member Silvester managed to come up with some code which was able to output software-timed serial data at 31250bd from the SC/MP SIO pin, something we had assumed was just impossible.

I think if you are looking at asynchronous serial data -reception- then the best approach is probably still to use a UART.
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Old 26th Jan 2023, 7:18 pm   #24
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Default Re: Advanced Mk14 Enhancements

Yes I had assumed it would be a lot slower than that, I suspect you could not read in data at that rate
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Old 26th Jan 2023, 10:21 pm   #25
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Default Re: Advanced Mk14 Enhancements

It's quite possible to use Sin/Sout to receive/transmit at 9600 baud, albeit using two bits. But 4800 baud (and lower) is easily done using one stop bit. Attached extract from code I use to perform automatic serial dialogue with host computer from my Elektor SC/MP clone. If you need to constantly poll UART chip for activity you may as well just use on chip SC/MP serial port
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File Type: zip serial.zip (978 Bytes, 24 views)
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Old 26th Jan 2023, 10:37 pm   #26
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Default Re: Advanced Mk14 Enhancements

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If you need to constantly poll UART chip for activity you may as well just use on chip SC/MP serial port
The 8154 does actually have an INTR pin which in theory could be used by an offboard UART to interrupt the MK14 on receipt of a serial byte but I have never looked into whether that follows all the way through - can the 8154 actually interrupt the SC/MP, or was that not implemented in the MK14 hardware..?
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Old 26th Jan 2023, 11:00 pm   #27
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Default Re: Advanced Mk14 Enhancements

The problem is that using 8154 INTR (wired to SC/MP sense A input) pointer 3 has to always have interrupt address loaded. Also interrupt is only generated from 8154 when port A is in strobed mode.
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Old 26th Jan 2023, 11:15 pm   #28
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Default Re: Advanced Mk14 Enhancements

The other problem is that when the 'New' OS is in use (which it invariably is because it is much better than the original OS) Sense-A is involved in the single-step feature which is hard-coded into the OS. If you aren't using the offboard single-step hardware, Sense-A has to be kept low to hold the single-step feature off.

Am I right in thinking that using an external UART would at least allow 'duplex' operation - reception and transmission of overlapping bytes at the same time, or does your code posted in #25 manage to cover that eventuality as well?
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Old 26th Jan 2023, 11:49 pm   #29
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Default Re: Advanced Mk14 Enhancements

My code is half-duplex, using Sense-B for CTS and Flag 0 for RTS. In the context I used it (uploading/downloading bytes and 'execute at address') it worked fine. In my experience only the 8251 UART had a nasty habit of resending bytes if CTS changes midway through byte.
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Old 27th Jan 2023, 1:05 am   #30
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Default Re: Advanced Mk14 Enhancements

I added a 'Microprofessor' I/O board to my Maplin Z80 system and it had an 8251 on it - horrible IC, I could only get it to receive reliably in the mode where it samples each bit more than once, which carried with it the penalty of having to use a higher baud clock frequency for any given baud rate. Not a fan.
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Old 27th Jan 2023, 1:23 am   #31
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Default Re: Advanced Mk14 Enhancements

I thought around 16x clock was pretty-common on UART's for Async serial, as otherwise it's difficult for receiver to get correctly in-sync (especially if there isn't an accurately-set crystal osc. etc at each end), if it can't bit-slide to work out the optimum (over)sample point.
The 6850 does support x1, x16 & x64, but I expect would have similar troubles at x1 if both tx & rx ends clocks weren't locked-together.

I would have thought a Z80(A)-SIO would be better suited in a Z80 system - Although Tatung Einstein etc. also used an 8251.
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Old 27th Jan 2023, 8:32 am   #32
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Default Re: Advanced Mk14 Enhancements

The 8251 does have a number of documented 'features'. That said I think the 8251A fixed some of them, I certainly use an 8251A on an extension board I designed for my Elektor Z80 board which works fine using x16. Have never tried the x1 setting - I assumed that was for synchronous serial coms
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Old 27th Jan 2023, 7:51 pm   #33
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Default Re: Advanced Mk14 Enhancements

Well I finally got round to finishing the schematic of my memory expansion for the MK14, schematic attached as a pdf.

I found a problem in my wiring while checking the schematic, I had A11 connected to NC on the ram, I never noticed as I've only checked a few locations using the MK14 monitor.

I've also not tested with orton view yet or the 4K IO page at F000-FFFF.

This plugs into the 8060 socket on the MK14.

I'm using the 74HCT193 as address latch and decoder for the high and low pages. The 74HCT257 provides tristate buffer of NRDS and NWDS to the MK14 which are disabled when NENIN input to the 74HCT193 carry input is high. This also controls access to MK14 memory from 0000-07FF or from the extended RAM which can be used to replace the PROMs in the MK14 memory map.

The low 2K of extended RAM is not available to the VDU, but writes can be made to this area if RAM is present on the OrtonView or other memory expansion on the MK14.
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File Type: pdf MK14_Memory_Expansion_Proto_v2.pdf (39.3 KB, 49 views)

Last edited by Mark1960; 27th Jan 2023 at 7:53 pm. Reason: spelling again
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Old 12th Feb 2023, 10:44 pm   #34
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Default Re: Advanced Mk14 Enhancements

Quote:
Originally Posted by Timbucus View Post
Yes I agree a new thread - the keyboard (4x10 matrix) was promised by Sinclair with BASIC but never delivered:

http://www.computinghistory.org.uk/d...Update-Letter/

There is a classified in Computing Today somewhere (Dec 1980 maybe) for an ad for an improved monitor with Alphanumeric Keyboard, labelled files and VDU routines Mr P.R. Trevellick, Oxford.
Interestingly, although SoC said in that letter that they were developing a 40way keyboard, attached to the 14way Ext. Keyboard connector, on the original advert they say this is for a 32-key (So presumably 8 x 4 matrix) one - that wouldn't be enough for a full Alphanumeric one, even without Enter / Space / Delete / Shift etc.:

https://rk.nvg.ntnu.no/sinclair/comp...s/mk14_ad1.jpg
https://rk.nvg.ntnu.no/sinclair/comp..._annotated.jpg
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Old 21st Feb 2023, 11:30 am   #35
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Originally Posted by Mark1960 View Post
...I'm using the 74HCT193 as address latch and decoder for the high and low pages.
The diagram shows an HC192 Mark (ie base 10), not sure if it matters since you're not using the counter, but would a 192 latch inputs above 1001? (page 0x0Annn to 0x0Fnnn ?)

The datasheet suggests (I think) its ok:
If a decade counter is preset to an illegal state or assumes an
illegal state when power is applied, it will return to the normal
sequence in one count as shown in state diagram.
(you're not counting so... presumably it holds the 'illegal state' )

Last edited by Phil__G; 21st Feb 2023 at 11:40 am.
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Old 21st Feb 2023, 5:56 pm   #36
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The diagram shows an HC192 Mark (ie base 10), not sure if it matters since you're not using the counter, but would a 192 latch inputs above 1001? (page 0x0Annn to 0x0Fnnn ?)
Sorry, thats a mistake, I reused the 74HC192 component and forgot to change the part description. I used 74HCT193 on my proto board, though I think HCT or LS 192 would also work but put the IORQ page at 0x9000 which might not be so convenient. I think I would avoid 74HC with INS8060 as the nmos outputs don’t seem to drive hard to 5v, though I have only seen that NADS has slow rise time above 2.5v.

The reset circuit using MAX818 is a little strange. If RAM chip enable is high the reset switch needs to be held for 1.6s then the watchdog circuit will pulse reset on the INS8060 low. If the RAM chip enable is pulled low by the pull down resistor, when ram is replacing the low 2k on the MK14, then reset switch will almost immediately pull the reset on the INS8060 low. I haven’t seen any problem due to this, its just a bit strange. Probably due to the MAX818 function to avoid pulling reset during a memory write, though the datasheet doesn’t indicate this effect on the watchdog circuit.
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Old 26th Feb 2023, 7:54 pm   #37
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Default Re: Advanced Mk14 Enhancements

I should maybe note that the way I use NENIN to disable the 74HCT257 leaves a risk that the RAM from 0 to 07FF can still be corrupted when NENIN is raised, even if the write protect is enabled, due to the pull down on the chip enable. I think it can only happen if the 8060 is writing to this address range when NENIN is raised, which it shouldn’t be doing anyway if this is simulating prom. I still haven’t tested this with ortonview yet, just noting this as a caution.

Last edited by Mark1960; 26th Feb 2023 at 7:55 pm. Reason: Added caution
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Old 7th Mar 2023, 11:00 pm   #38
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Default Re: Advanced Mk14 Enhancements

Continuing on the broad theme of enhancements to the MK14, talk of cassette tape interfaces reminded me of an idea which was first brought up by forum member Gertk64(?) who hasn't been around for a while as far as I know.

The original SOC cassette interface, by default, outputs silence. When it is operating it generates a train of short, and shorter, beeps. When it's finished sending, it sends more silence.

The drawback with this signalling method is that the cheap cassette recorder likely to be on the receiving end of this will probably have ALC, so during the silent lead-in the record level gain will drift higher and higher until suddenly, it is hit with the first of a train of loud beeps.

It takes the ALC a finite amount of time to react to the sudden presence of loud audio, so initially the record level gain will be too high, and this could lead to bad distortion on the first few recorded bits which in turn may make it difficult to load the code back in.

Later Sinclair machines dealt with this by sending out a long train of steady tone, not data, for the ALC to settle down on first, hence the characteristic 'weeeeeeeeee-ick' sound of a ZX Spectrum program recording.

The idea brought up by Gert was to invert the save-data stream out from the MK14 before sending it to the standard cassette interface so that instead of generating silence interrupted by short bursts of audio tone, the cassette interface would generate a steady tone interrupted by short bursts of silence. The normally-on tone would give the ALC a steady state audio signal to settle on, so that by the time the first data bit was sent the record level would be properly adjusted.

Going the other way, the data-out stream from the cassette interface would need to be inverted before being sent to the MK14, and on replay the cassette recorder would need to be already 'playing' the long lead-in tone at the moment the load-from-cassette routine was invoked.

It was never an issue with 'posh' cassette recorders which had manual level controls and nowadays even the simplest audio recorder on a modern digital device will offer manual control of the record level, but as a solution to a historic problem, I liked it.

Along similar lines, there was a suggestion of keeping the audio tones as they originally were (silence interrupted by short beeps) but mixing a steady ultrasonic tone in with them, the idea being that the microphone amplifier / ALC circuit would 'see' the ultrasonic tone and level-adjust to that, but the tone would not actually be recorded on the tape. Whether this worked or not would, I suspect, be very dependent on the individual tape recorder and for one with AC bias there would be the potential for the ultrasonic 'carrier' frequency to mix with the bias frequency to create an unwanted audible tone.

I have no idea whether either of these ideas were ever actually tried - I'm sure the 'tone inversion' idea would work, not so sure about the high frequency carrier idea.

Last edited by SiriusHardware; 7th Mar 2023 at 11:06 pm.
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Old 18th Apr 2023, 11:49 pm   #39
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Default Re: Advanced Mk14 Enhancements

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I'm using the 74HCT193 as address latch and decoder for the high and low pages.
Mark, could you explain the use of the 193 as page 0 and F decoder please, I can see the obvious NADS latching of A12-15 to the 193 outputs, but I dont get NENIN connected to the 'down' clock or how CO/BO work as page 0/F selects, the datasheet suggests that they're momentary lows (half a clock?) - I feel I'm missing something and this 193 idea seems incredibly useful I should stick one on a breadboard with a dipswitch and try it, but asking seemed easier
Ta v much
Phil

Last edited by Phil__G; 18th Apr 2023 at 11:55 pm.
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Old 19th Apr 2023, 2:04 am   #40
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Default Re: Advanced Mk14 Enhancements

The borrow and carry outputs are active low, but only active if the count down or count up inputs are low. So long as at least one of the borrow and carry inputs are held low the counter will not count. The way I have it, the count up input is held low, to stop the counter from counting, then the count down input can be used as an active low enable for the borrow output.

In my daughter board I thought I could use NENIN to enable the page 0, then the display can disable the ‘257 to disable access to the MK14 memory while the display is reading from memory. This is still not tested with a display though, I’ve not had much time to play lately.
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