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Old 28th Jan 2023, 1:49 pm   #20
DrStrangelove
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Join Date: Jan 2023
Location: Neath, Port Talbot, Wales, UK.
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Quote:
Originally Posted by jjl View Post
Jeremy

I've seen mention of process 50 and other numbers with regards to FETs on this forum. Please could you give a brief explanation of the meaning of these process numbers.

John
Having worked for Siliconix for knocking on for a decade it would appear that "process xx" corresponds to "geometry" in the Siliconix FET catalogues of yore.

Back then FETs were tested in wafer form at "die sort" where the entire wafer (an enormous 3" diameter) was tested for function and various parameters.

I looked up the 2n3819 and it appears that it was sourced from two geometries: NH and NRL which would explain why different batches might have different spreads of IDSS etc.

Siliconix do not make small signal FETs anymore following the closure of the Santa Clara fab.

As to the question of the surface mount part differing from the through hole part, they would use the same die sorted on the same parameters so no improvent there then.

Further details of "process xx" are available in an ONSEMI/On Semi/Fairchild application note AN-6609 from the dear dead days of 1977.

https://www.onsemi.com/pub/collateral/an-6609.pdf

Then again if you were prepared to pay for it, Siliconix would create a special device spec with tighter test conditions.

It saddens me to see various devices carrying such numbers asked about on various boards when there's no means of figuring out what the baseline device was now the factory has been closed for more than 30 years.

So if you see a device with "WNxxx" and the Siliconix logo, it came from Swansea.
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