Quote:
Originally Posted by Timbucus
Quote:
Originally Posted by Mark1960
Quote:
Originally Posted by SiriusHardware
The CE1 of the 0Fxx range has three distinct levels. I don't like that at all.
|
Is this chip enable direct from the address bus? The A0 in previous posts shows similar levels. As the RAM chips have two chip enables this might not be a problem if the other chip enable is high at those times but its also never good to have indeterminate signal levels. Maybe adding pullups to the most significant address lines would help. |
Great minds obviously... |
The CE1 for the Bxx memory comes straight from A10, for Fxx its via a 74LS04 inverter. If the bus is tristate that would mean the input to the inverter is floating so its not impossible to imagine wierd logic levels on its output, although I thought that was more an issue for CMOS inverters.