Quote:
Originally Posted by SiriusHardware
The CE1 of the 0Fxx range has three distinct levels. I don't like that at all.
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Is this chip enable direct from the address bus? The A0 in previous posts shows similar levels. As the RAM chips have two chip enables this might not be a problem if the other chip enable is high at those times but its also never good to have indeterminate signal levels. Maybe adding pullups to the most significant address lines would help.