Re: Mk14 vdu
Karen, thanks for the latest try to get things running smoothly. As Tim has already test driven it and found that it didn't seem to make a difference, I haven't tried it myself.
One thing I did do was this:
-OrtonView with the latest mainstream firmware, enabled, displaying 0Fxx and 0Bxx
-CPU kept out of harm's way by executing a tight loop in I/O RAM (0880) so that the only thing accessing the 0Fxx and 0Bxx RAM areas (and therefore activating the chip enables for those areas) should be OrtonView
Attached images are both captured at 1V/Div with 0V lined up on the first thin horizontal graticule line.
#1: Sample portion of CE1 of the 0Bxx RAMs
#2: Sample portion of CE1 of the 0Fxx RAMs
The CE1 of the 0Bxx range has only two logic levels, enabled and not.
The CE1 of the 0Fxx range has three distinct levels. I don't like that at all.
I'm wondering if we need to try putting 'real' tristate buffers between the address output pins on the PIC and the SC/MP address bus, or less drastically, try pulling at least the high bits A8-A11 either high or low.
If we insert buffers, that implies the need for an enable signal for those buffers and unfortunately we don't have any pins left over for that.
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