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Oh by the way, if you are feeling particularly enthusiastic, how about tracking the address, data and control buses to the fingers on the underside of the top edge connector? SOC never did bother to do that, but it would have been a very sensible thing to do especially after the introduction of the VDU, which required all those connections.
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Hmm.. That probably wouldn't be to hard since quite a lot of those lines go up to the RAM/IO anyway. Do you know if there is a "definitive" mapping (i.e. order of pins) or was it just left to user whim?
I just checked my circuit with 6561 RAM chips by changing JP1 on the schematic I posted earlier and it works fine. One slight difference is all the memory locations reset to FF rather than random values on initial power up which is interesting but unimportant. The "add on" ram chips U6 & U7 work too. I wasn't able to test the RAM/IO because due to the heatsink the chip doesn't go into the socket
- on the new PCB I've moved the RAM/IO chip to give more room for the heatsink. It only involved removing and relaying about 50 tracks!