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Old 6th Dec 2021, 12:39 am   #4
Phil__G
Octode
 
Join Date: Mar 2011
Location: North Yorkshire, UK.
Posts: 1,122
Default Re: A new Verilog core SC/MP - checking against real timings

Sounds fascinating Dominic
Quote:
Originally Posted by dominicbeesley View Post
Is there a "favourite" NIBL program that I should try running on this to exercise it?
If you download the PICLV2 document (PICLV2files.zip) there are several NIBL demo programs in there for copy-&-paste, including the BASYS monitor written in NIBL. The Calendar keeps it pretty busy. Its on http://philg.uk

Your FPGA scamp might be the answer to a 32k system running Karen's PAGE2.SYS
Cheers
Phil

Last edited by Phil__G; 6th Dec 2021 at 12:48 am.
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