[G0HZU_JMR]

Could be. The 4.7pF cap also really helps to manage the negative resistance at the probe input as demonstrated in the video.

I've just built a 'real' version of the (drain) boostrapped JFET buffer amplifier using a 2N5485 and a MMBTH10 BJT. I've added the necessary bias components and run it from an external PSU. It is nearly all in SMD and it is very small! I have built this in a way that is quite different from the Bob Pease probe. I have used a layout that minimises stray capacitance to free space. So there are no 'wires' or component legs anywhere. It is point to point SMD construction under a microscope and the whole thing is about 8mm x 5mm in size. I think this is why I get the predicted input capacitance of about 0.2pF.

I have cheated slightly because I have fed the gate bias in via the VNA bias tee so I have lost the (0.05pF) capacitance of the SMD input shunt resistor. But see the result below. It's a bit boring because it agrees very well with the previous (simulated) version of the circuit where I use s parameter models for the transistors.

This result makes sense to me because I have been able to (almost) cancel the input Cdg and Cgs capacitance of the 2N5485 JFET with the boostrap and a 10k source resistor that mimics a current source. I've tried very hard to minimise any free space capacitance.

Note that if I measure a precision 0.3pF 0603 packaged SMD microwave capacitor in the place of this circuit my VNA/jig measures a flat 0.35pF out to 200MHz. The jig has some fringing capacitance so this adds to the result.