Re: Mk14 vdu
The address drive from the SOC VDU is 'gated' by proper tristate buffers, whereas the PIC I/O pins most likely swim high when configured as inputs.
It seems as though the capacitors delay the rise of the address lines for just long enough for SC/MP NRDS to end, in the specific cases where NENIN rises smack in the middle of an SC/MP NWDS pulse.
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