Quote:
Originally Posted by Slothie
So what aspect of the timing is changing that these additional capacitors make?
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They should be delaying the rise of A8 to A11 when NENIN is raised to kick the SCMP off the bus. They need to be held at the logic level that was being driven by the SCMP longer than the time it takes for NWDS to be pulled high.
Timing of NWDS rise would be dependent on the release time of the SCMP and the pull up resistor, but I don’t think that could be reduced much below 4.7k without loading the SCMP output too much.
It seems likely that the Orton View PIC drive of A8 to A11 is pulling these address lines high a bit faster than the MK14 vdu drivers.
Maybe scoping A11 and NWDS with charset writing to 03xx could show the difference between Orton View and MK14 vdu.
A better understanding of the PIC output drive might still make a software fix possible, which would be the nicest solution.
Another possibility could be to buffer the PIC address drive with a couple of 74ls365s, with enable gated by NENIN high and NRDS low, but this is not in keeping with the simplicity of Karen’s design.