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I presume "when I assert NENIN low" is a typo and you mean "NENIN high"?
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You are correct, you assert NENIN high to boot the SC/MP off the bus.
Before we go any further: can we try slugging NRDS and NENIN using small capacitors e.g. 470pF just to be certain that fast edges on the PIC outputs is not causing all the trouble we're seeing? It is shocking how much trouble fast edges can cause.
I've done a careful study of the timings of my code relating to NENIN transitions. They look okay to me in terms of giving the SC/MP adequate time to get off the bus. There is opportunity to increase this margin a little, but that will lead to a slowing of the Mk14.
ANALYSIS
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t1 = NENIN high to address bus drivers low impedance
t2 = NENIN high to first read cycle NRDS low
t3 = Address bus high impedance to NENIN low
Note: 1~ = 250nsec = 0.25usec
1 (Bus acquisition in preparation for buffer pre-charge)
t1 = 15~ = 3.75usec
t2 = 25~ = 6.25usec
2 (Bus release after buffer pre-charge)
t3 = 21~ = 5.25usec
3 (Bus acquisition in prep. for main display region)
t1 = 21~ =5.25usec
t2 = 100+~
4 (Bus release after main display region)
t3 = 13~ = 3.25usec
The following occur during text generation
5 (Bus release prior to text rendering)
t3 = 9~ = 2.25usec
6 (Bus re-acquisition following text rendering)
t1 = 14~ = 3.5usec
t2 = 34~ = 8.5usec
The following occur during graphics generation
7 (Bus release prior to graphics rendering)
t3 = 13~ = 3.25usec
8 (Bus re-acquisition following graphics rendering)
t1 = 18~ = 4.5usec
t2 = 38~ = 9.5usec