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General Vintage Technology Discussions For general discussions about vintage radio and other vintage electronics etc. |
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5th May 2017, 7:08 am | #21 |
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Re: The dual-gate MOSFETS are going away
Large crates of 'junk' is a prerequisite for creativity. It's the only way I can make progress. Without my junk I'd spend my whole life ordering stuff.
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5th May 2017, 12:54 pm | #22 |
Dekatron
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Re: The dual-gate MOSFETS are going away
I think that would be very hard to do. I worked at Plessey and remember both the silicon and the gallium arsenide areas at Caswell. You'd need a pretty good cleanroom(s) and be prepared to work with various chemicals which are quite hazardous.
Isn't (wasn't) there a company operating in the Swindon area (presumably a left over of Plessey Swindon) that was doing small-quantity runs of customer specialist IC's? I think that there's also a company somewhere on the south coast operting under the Plessey name who seem to be involved with small quantity semiconductor production. Maybe some small company exists somewhere who could do small quantity production of MOSFETs, but what the cost would be.... B
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5th May 2017, 1:10 pm | #23 |
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Re: The dual-gate MOSFETS are going away
I have actually had stuff I've worked on fabbed as part of my university course and the cost of a one off was around £20k for a few thousand CMOS gates. That was crazy discount rate for education as well.
The expensive bit was actually the bonding and packaging and the fact you need at least 10 made and you're lucky if 2 work. We had three out of 8 work which people were surprised at. Best chance for something cost effective is second sources such as CDIL in India but you'll only get per device cost reasonable with a massive run. |
5th May 2017, 1:30 pm | #24 |
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Re: The dual-gate MOSFETS are going away
Do any Universities have small-scale manufacturing labs that might be able to do this sort of thing? It would of couyrse be necessary to persuade someone to make a set of masks available, if they still exist. In the mid-1970's Plessey sent our team of engineers on an integrated circuit design course at what was then Enfield Polytechnic, where we were instructed in the then-current processes (thick film, thin film, silicon). as well as the theory, we had practical lab sessions where we applied photo resist to the silicon wafers, exposed and developed the resists, loaded the wafers into the boats and loaded them in the diffusion furnaces etc., and diced and packaged the manufactured chips. It was great fun, especially as how this was after we had designed a set of ten custom ICs for a phase locked loop weapons guidance system (all of which worked first time)! I do remember a lecturer saying that they had to expose the masks for anything that required high resolution in the wee small hours of night, as otherwise the vibrations from traffic would ruin the work.
Last edited by emeritus; 5th May 2017 at 1:35 pm. |
5th May 2017, 2:17 pm | #25 |
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Re: The dual-gate MOSFETS are going away
I very much doubt they do these days. We had to subcontract ours out to a defence company.
That sounded more fun that sitting in front of Cadence Virtuoso all day drawing squares on a rancid old Sun box |
5th May 2017, 7:16 pm | #26 |
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Re: The dual-gate MOSFETS are going away
That was in the days when "cut and paste" was used literally, and IC layouts were designed using very large sheets of mm graph paper or stable grid , a 6H pencil, a plastic rubber and an eraser shield. Individual elements were optimised and then photocopied for use as building blocks which could be manually positioned to optimise the overall layout. The then state of the art Xerox copiers were not sufficiently accurate as they had slightly greater magnification in one direction than the other, so we had to draw circuit blocks out on stable grid tracing paper and have dyeline contact prints made, then cut out the shapes with scalpel and steel ruler. To have the masks made, the X-Y co-ordinates of the corners of each element of each layer had to be written onto coding sheets that were sent off to Compugraphics in Glenrothies, who cut the Rubyliths. When the special production line at Swindon was destroyed in a fire, and there was no second source supplier remaining for the obsolescent technology we were still using, we had to re-design for the replacement process. For that we did not have to fill out any coding sheets as we were able to use another company's facilities to enter the co-ordinates onto computer tape by positioning crosshairs over each corner and clicking a button. as they were busy themselves, it meant starting work after they had gone home, and, as it was apparently not feasible to leave us a set of keys to lock up, when we were finished (usually at about 3 AM), we had to climb out of the window and pull it shut behind us. I did wonder what would have happened if a policemen had happened to come along as we were emerging from the shrubbery, but there was never anyone about. Happy days!
I believe that these days there are programs that take you straight from the logic diagram to the masks, so there is less opportunity to actually lay out anything yourself. Last edited by emeritus; 5th May 2017 at 7:24 pm. |
5th May 2017, 8:05 pm | #27 |
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Re: The dual-gate MOSFETS are going away
Interesting story - better times if you ask me.
In the mid-late 1990s when I had to do that we had nothing quite that fancy. We started with Verilog and did simulation runs then cluelessly slap predefined gates and MOS devices down on substrate on the machine and cross fingers. Can't remember the exact process but there was a bunch of STI files which contained test cases and stimulus so you designed the whole subsystem in verilog and then tested the IC with the STI files. Eventually the tests passed and you ran it through DRC and check out and it generated a couple of rather large files we tar'ed off onto tape and sent for fab. A couple of weeks later we got a box of legged lumps of good old purple ceramic and gold back to play with. Kind of wish I'd stayed in that space rather than moving into IT. I'm doing the above now but with C# at a slightly higher level of abstraction and a better turnaround time Not sure about auto-routing ICs etc but the FPGAs on the market killed off a lot of the ASIC work out there. I saw this coming if I'm honest and bailed out into software. When I was working for a defence contractor in the early 00's, they were shipping PPC cores and entire subsystems on FPGAs and no sign of an ASIC at all so I made the right move I think. This is what is possible these days. Open this in Chrome on a half decent PC only: http://www.visual6502.org/sim/varm/armgl.html Edit: found a screenshot from my (very short) era: Last edited by MrBungle; 5th May 2017 at 8:14 pm. |
6th May 2017, 12:08 am | #28 | |
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Re: The dual-gate MOSFETS are going away
Quote:
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6th May 2017, 11:51 am | #29 |
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Re: The dual-gate MOSFETS are going away
I like to sit on the line, learn from the past and apply it to the future
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